Having problems with Verilog wires

Question

For the record, I'm a complete newbie to Verilog. I am writing a module that uses several bi-directional buses.

inout wire [KEY_SIZE-1:0] prevKey; inout wire [TAG_SIZE-1:0] prevTag; inout wire [KEY_SIZE-1:0] nextKey; inout wire [TAG_SIZE-1:0] nextTag; 

I know how I read things from the bus, but how do I write something on it? If I use the assignment operator for reg , will the reg value depend on when the new data gets on the wire? Is it dealing with an inout port that is worth the hassle, or do I just need to make an input and output bus for each?

Answer 1

If I use the assignment operator in reg ...

This statement does not really make sense, you do not perform assignments in the registries, you assign wires.

A simple example of bringing inside a wire:

 inout wire bidir_wire; reg drive_value; reg drive_enable; reg something; assign bidir_wire = drive_enable ? drive_value : 1'bz; always @(posedge clk) begin drive_value <= ... ; //assign a drive value based on some criteria drive_enable <= ...; something <= bidir_wire; //do something with the input value end