L1 and L2 bets on the SimpleScalar model

Question

I simulated 4 different binaries in the SimpleScalar simulator, and for each binary, the LIM level of the unified transmission rate is greater than the data transfer rate L1.

In my assignment I have to do some analysis. The first thing that comes to my mind is the L2 speed, which should be less, because it has a higher hierarchy level and is larger than the L1 cache.

In addition, as far as I know, L2 is referenced only when there is a miss in the L1 cache. From my point of view, L2 should have data that L1 does not have a lot of time, so its throughput should be less.

However, the results are not close to expected.

For instance,

• L1 Data Miss Rate: 0.0269
• L2 Unified Miss Rate: 0.0566

The skip rate is defined as misses / references for caching.

What is wrong with my approach? Why is the L2 skip rate greater than L1?

Answer 1

Hit / miss bets only consider access to data that tried to use a particular cache. Therefore, if the data that you are using is already in the register, there is no need to even check the L1 cache, so L1 does not register any hit or miss. Similarly, if data is found in L1, L2 does not record any hit or miss. The frequency of skips for L2 is mainly (the data for 1 time was not in L2) divided by (the number of times that L2 was accessed) or equivalent (# times the data was not in L2) divided by (the number of times when the data was not in L1).