Cannot Modelsim and GHDL reset vhdl custom signal types in vcd?

Question

I am trying to dump internal signals from a simulation done either with modelsim or with ghdl. Everything works fine using:

For modelsim, add vhdl sources and compile everything:

vsim -novopt work.uut_testbench vcd file ../uut.vcd; vcd limit 50000000; vcd add -r /uut_testbench/uut_core/*; run 6000 quit -sim 

For ghdl

 ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=work --work=work ./uut*.vhd ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=work --work=work uut_testbench ./uut_testbench --stop-time=6000ns --vcd=../uut.vcd 

I see simulation signals, but not all. Signals defined as

 Type InternalState is (Idle,Valid,Stalled); Signal sState,sPrevState :InternalState; 

excluded from vcd. This behavior is common between modelsim and ghdl.

I see the following line in ghdl vcd generation

 $comment sstate is not handled $end 

Modelsim just lowers these signals quietly

Is there a workaround? Alternative?

Answer 1

Try Tony Bybell gtkwave, in which you can assign enumeration spoofing to values ​​(the gtkwave manual in the sections "Quick Start", "Alias ​​Files" and "Attaching External Disassemblers"). Gtkwave is also compatible with the ghdl native (ghw) waveform format. See Gtkwave on SourceForge for a guide and download links for binaries for W32 and Mac. It should also be available through any Linux distribution.

Answer 2

Your simulator does not know how to represent its type of InternalState using scalar or vector variables available in the value change dump file. If you use, for example, the std_ulogic vector to represent your states, they will be displayed in the VCD file. A good waveform viewer allows you to replace the state encoding with state names. Gtkwave supports this, as user 1155120 has already pointed out. IEEE Std 1800-2012 describes in section 21.7 VCD files and their limitations.