Implicit rule issues in make

Question

I have the following directory structure

(root) / / \ \ / | | \ src obj include bin 

I would like to use an implicit rule to compile all .cc files in root\src files to .o in root\obj .

This is my makefile:

 basedir = . incl = ${basedir}\include obj = ${basedir}\obj src = ${basedir}\src lib = ${basedir}\lib bin = ${basedir}\bin CXX = gcc LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \ -lSDL_mixer LDFLAGS = -L${lib} objects = $(addprefix ${obj}\, GameObject.o PhysicalObject.o \ Terrain.o Timer.o main.o ImageLoader.o Player.o ) sources = $(addprefix ${src}\, GameObject.cc PhysicalObject.cc \ Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc ) Cyborg : ${objects} ${CXX} ${objects} -o ${bin}\Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS} ${obj}\%.o : ${src}\%.c ${CXX} ${src}\$^ -c -o ${obj}\ $@ .PHONY: clean clean : rm ${bin}\Cyborg.exe ${objects} 

The error I get is make: *** No rule to make target .\obj\GameObject.o, needed by Cyborg. Stop. make: *** No rule to make target .\obj\GameObject.o, needed by Cyborg. Stop.

Any idea what goes wrong? I am new to makefiles, so this can be very obvious.

Answer 1

Applying all the ideas from the comments (and adding a couple of your own trivial ones), we get:

 basedir = . incl = ${basedir}/include obj = ${basedir}/obj src = ${basedir}/src lib = ${basedir}/lib bin = ${basedir}/bin CXX = g++ LDLIBS = -lstdc++ -lmingw32 -lSDLmain -lSDL -lSDL_image -lchipmunk -lSDL_ttf \ -lSDL_mixer LDFLAGS = -L${lib} objects = $(addprefix ${obj}/, GameObject.o PhysicalObject.o \ Terrain.o Timer.o main.o ImageLoader.o Player.o ) sources = $(addprefix ${src}/, GameObject.cc PhysicalObject.cc \ Terrain.cc Timer.cc main.cc ImageLoader.cc Player.cc ) Cyborg : ${objects} ${CXX} ${objects} -o ${bin}/Cyborg.exe -L${lib} ${LDFLAGS} ${LDFLAGS} ${obj}/%.o : ${src}/%.c ${CXX} $^ -c -o $@ .PHONY: clean Cyborg clean : rm -f ${bin}\Cyborg.exe ${objects} 

What does Cyborg do with this makefile?

Answer 2

It will probably take several iterations.

Try some simple rules in increasing order of complexity and let us know the results:

 ./obj/GameObject.o : ./src/GameObject.cc @echo trying to build $@ from $< ./obj/GameObject.o : ./obj/%.o : ./src/%.cc @echo trying to build $@ from $< $(objects) : ./obj/%.o : ./src/%.cc @echo trying to build $@ from $< ./obj/%.o : ./src/%.cc @echo trying to build $@ from $< 

Answer 3

 ${obj}\%.o : ${src}\%.c --> ${obj}\%.o : ${src}\%.cc 

Answer 4

I had a similar problem with GNU make. Try to enter rules for your objects:

 $(obj)\GameObject.o: $(src)\GameObject.cc $(obj)\PhysicalObject.o: $(src)\PhysicalObject.cc # and so on for each object