Homework?
In most caches, all requests are sent to L1 cache, and then, only after they have been identified as skipped, go to L2. And so on.
Or:
In 100 hits
Time spent on L1 hits = time to reach cache L1 * Attack speed of cache L1
Time spent on skipping L1 that goes to memory = skip speed of L1 cache * (time to wait for L1 cache + time to go to memory)
Total time = Thit * Phit*100 + Pmuss*100 * (Thit + Tmiss) = Thit * (1-Pmiss)*100 + Pmiss*100 (Thit+Tmiss) = Thit * ( 1-Pmiss+Pmiss ) * 100 + Pmiss*100*Tmiss = 100* (Thit + Pmiss*Tmiss)
etc. if you have L2.
those. they cancel.
Now there are AES caching systems, or at least they were when calls were sent both to the cache and to the memory at the same time. In such systems
Tavg = Phit*Thit + Pmiss*Tmiss.
but they are not common. They tend to lose energy since you started accessing L2 or main memory, which you probably won't need.
I call the first reverse cache and the second cache.
(Since then, I learned that some of my colleagues call this last case, when access is simultaneously sent both to the cache and to memory, “speculative cache allows memory access.” This is not an unreasonable use of the term “speculation”, but which can also be confused with “speculative cache misses,” as was obtained, for example, by a branch prediction machine. Consider two cases: (1) a machine without branch prediction, not speculative execution, a machine, an instruction, a memory reference, is not speculative, That's why we just think about whether to send this access only for caching or also in memory. (2) a machine with branch prediction or other forms of speculative execution. such a machine, the actual memory operation is speculative. These two can be combined: a speculative instruction, which we we don’t know yet what it’s actually going to execute, it can create access to memory, which may or may not be speculatively sent to memory until it is defined as a cache miss.)