CPU Command Reordering Tracking

Question

I learned a few things about reordering instructions by processors and the Thomasulo algorithm.

In an attempt to understand this section more, I want to know if there is any way (get a trace) to see the actual dynamic reordering performed for this program?

I want to provide an input program and see the "trace of command execution out of order" of my program.

I have access to an IBM-P7 machine and an Intel Core2Duo laptop. Also please tell me if there is a simple alternative.

Answer 1

You do not have access to the actual reordering performed inside the CPU (there is no well-known way to enable tracing). But there are some reordering emulators, and some of them can give you useful tips.

For modern Intel processors (Core 2, Nehalem, Sandy, and Ivy), Intel has an Intel Architecture (R) Architecture Analyzer (IACA). On the home page http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

This tool allows you to see how some linear piece of code will be divided into micro-operations and how they will be planned in port execution. This tool has some limitations, and this is just an inaccurate model for reordering and executing the u-op CPU.

There are also some "external" tools for emulating the internal components of the x86 / x86_84 CPU, I can recommend PTLsim (or the resulting MARSSx86 ):

PTLsim models a modern x86-64 non-x86-64 super scalar processor core at a customizable level of detail ... right down to the RTL level models of all the main piping structures. In addition, all microcode, a complete cache hierarchy, a memory subsystem, and supporting hardware devices are simulated with true loop accuracy.

But PTLsim models some “PTL” processor, not a real AMD or Intel processor. The good news is that this PTL Out-Of-Order , based on ideas from real kernels:

The main microarchitecture of this model is a combination of design features from Intel Pentium 4, AMD K8 and Intel Core 2, but includes some ideas from IBM Power4 / Power5 and Alpha EV8.

In addition, the arbeit http://es.cs.uni-kl.de/publications/datarsg/Senf11.pdf states that the JavaHASE applet is able to simulate various simple processors and even supports the Tomasulo example .

Answer 2

Unfortunately, if you do not work in one of these companies, the answer is no. Intel / AMD processors do not even plan the (macro) instructions that you give them. First, they transform these instructions into micro-operations, and then plan them. What are these micro-instructions and the whole process of reordering instructions is a carefully guarded secret, so they don’t want you to know what is going on.