The traditional 8088/86 had / had a memory control signal, which is essentially another bit of the address associated directly with the instruction. A control signal sharing access to I / O and memory creates two separate address spaces. Unlike CS, DS, etc., creating separate memory cells inside the chip (before deleting the external memory space). Other processor families use the so-called memory I / O.
Nowadays, controllers / memory systems are torn inside and outside the chip in different ways, sometimes, for example, with many control signals that indicate a command with data, filling cache lines, writing via vs write back, etc. To save on the external circuit, the memory is displayed inside the chip and, for example, the dedicated rom interfaces, separate from ram, etc., are on the edge, much more complicated and separate than the I / O space against the memory space of the old 8088/86.
The output and instruction and several family members change whether you are accessing I / O or accessing memory, and traditionally the interrupt controller was a chip that decrypted the memory bus looking for I / O access with a dedicated address for this device. Decades of backward compatibility later, and you have the real code you're looking at.
If you really want to understand this, you need to find the data tables for the device containing the interrupt controller, which is likely to be combined with a bunch of other logic on a large support chip. Other tables may also be required.