Create and build

Question

It was interesting to me...

When you make changes to file1.c or file2.c or file1.h , the following makefile will recompile just what you need (which is nice)

 # Link to executable result: file1.o file2.o gcc file1.o file2.o -o result23 # Assemble to .o object files file1.o: file1.s gcc -c dist/file1.s file2.o: file2.s gcc -c dist/file2.s # Compile to .s assembly files file1.s: file1.c gcc -S file1.c file2.s: file2.c gcc -S file2.c 

However, when I move the constructed object to another directory, it is restored all the time, regardless of whether only one file content has been changed.

 # Link to executable result: file1.o file2.o gcc file1.o file2.o -o result23 # Assemble to .o object files file1.o: file1.s gcc -c dist/file1.s mv file1.o dist file2.o: file2.s gcc -c dist/file2.s mv file2.o dist # Compile to .s assembly files file1.s: file1.c gcc -S file1.c mv file1.s dist file2.s: file2.c gcc -S file2.c mv file2.s dist 

This seems to be happening because make does not know where the .o files are.

With this a few questions:

• Can they access environment variables? If so, can you give an example?
• Is it possible to get information about incremental strings when the distribution directory is different from the current directory?

Answer 1

To fix your build, you need to do something like this:

 # Link to executable result: dist/file1.o dist/file2.o gcc dist/file1.o dist/file2.o -o result # Assemble to .o object files in main directory dist/file1.o: dist/file1.s gcc -c dist/file1.s -o dist/file1.o dist/file2.o: dist/file2.s gcc -c dist/file2.s -o dist/file2.o # Compile to .s assembly files dist/file1.s: file1.c gcc -S file1.c -o dist/file1.s dist/file2.s: file2.c gcc -S file2.c -o dist/file2.s 

You can use environment variables in make too, too .. although I'm not sure how this relates to the core of your question: just use something like this, install BUILDDIR and OBJDIR and create a make file like this:

 $(BUILDDIR)/foo : $(OBJDIR)/bar.o g++ $(OBJDIR)/bar.o -o $(BUILDDIR)/foo 

Although you can make this (and my fixed makefile) more enjoyable using automatic variables :

 $(BUILDDIR)/foo : $(OBJDIR)/bar.o g++ $? -o $@ 

Answer 2

1, you can access your environment variables just like any other variable; e.g. $(TERM)

2, just change the make target to include the target directory:

  dist/file1.o: file1.s gcc -c dist/file1.s -o $@ 

Where $@ is an implicit variable representing, for the purpose, dist/file1.o in this example.