Verilog combinatorial hardware multiplication

Question

Suppose I have such a multiplier code,

module multiply( output [63:0] result, input [31:0] a, input [31:0] b ); assign result = a * b; endmodule 

This creates a lot of gates.

Which preferred method should be used to implement a combinatorial factor?

Answer 1

Equipment multipliers are big, you just need to live with it!

Multipliers will increase as the width of the input bits increases. Therefore, if you do not need the full 32 bits on one of your operands, then reducing this size to a minimum will reduce the size of the resulting equipment.

If you multiply by a fixed number, I think the compiler can do some optimizations to limit the size of the hardware. Or you can use different coding schemes for a fixed number, such as CSD , which will reduce the number of adders in the multiplier, which will further reduce its area.

If you need a lot of multipliers and have a fast clock, perhaps you can reuse a single hardware multiplier for many calculations. This means that you need to write some control / pipelining logic to plan the multiplication, and you may need some memory, but it can save you the whole area. In this case, you plan to create a datapath with a mini DSP.

Answer 2

If you can refuse the combinatorial requirement, you can do the multiplication using the adder and accumulator , if the speed is not high and you can process the operands for several hours. Some processors with low power / low cost / small area do not have specialized ISA multiplication instructions or the asm multiplication instruction is changed to the operations of adding an interface instruction by the decoder in addition to microcode operations.

If you used this methodology, you would have to create additional signals for the hand-shake data, since the output does not have a longer valid 1 cycle after the input settles.

Answer 3

The generated verilog factor may not be optimal. There are many studies in the field of evvective multipliers and adders. And here is one of the pretty versatile and good add / mul generators: http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html

This page contains descriptions of many low-lewel add / mul implementations.