VHDL difference between => and <=

Question

I keep forgetting and it's hard to find the answer in a textbook or on the Internet.

Answer 1

Well, <= is the destination.

 signal <= A or B; 

=> - the syntax used for case statements: (Stolen from http://www.cs.umbc.edu/portal/help/VHDL/sequential.html )

 case my_val is when 1 => // This is kind of like how the : operator is used for switch in many languages a:=b; when 3 => c:=d; do_it; when others => null; // do nothing end case; end case; 

=> can also be used in array assignments

 myVector <= (1=>'1', OTHERS=>'0'); -- assigns ('0','1','0','0') to "myVector" 

Source: http://www.eda.org/comp.lang.vhdl/html3/gloss_example.html

Answer 2

<= represents the assignment operator, while => used in the case statement, for example:

 case sel is when "01" => line <= "1"; when others => line <= "0"; end case 

sets line to "1" if sel is "01" and "0" otherwise.

=> also used in structural code on port maps.

Answer 3

The <= operator is known as the signal assignment operator to emphasize its true purpose. The signal assignment operator defines the relationship between the signals. In other words, the signal on the left side of the signal assignment operator depends on the signals on the right side of the operator. (Source: Digital_Mclogic_Design Brian Miles, Section: Signal Assignment Operator: "<=", p. 339). I could not find anything specific in the => operator.

Answer 4

A means remembering when to use => and when to use <= you should think like it should.

"<=" as the destination for the signal as the target (for the variable, it is :: ").

Examples:

 y <= a + b + c; --y is a signal v := a + b +c; --v is a variable 

"=>" as a mapping .

Example for explicit component mapping (recommended IMHO style):

 my_instance : my_component port map( port1 => my_signal1 ); 

Example for explicit function mapping (useful when parameters are not trivial):

 my_signal <= my_function(parameter1 => something1, parameter2 => something2); 

An example to explicitly display an array

 type array_type is array(0 to 1) of std_logic_vector(7 downto 0); constant my_array : array_type := (0 => x"AB", 1 => x"CD"); 

An example to explicitly display a record

 type record_type is record a : natural; b : std_logic_vector(2 downto 0); end record; constant my_record: record_type := (a => 0, b => "101"); 

The advantage of this style allows matching to be done in the order of your choice (not necessarily in the definition of a component / function ...). Moreover, in the specific case, an array with one element is required.

Finally, using the "=>" keyword others allows you to match all the other elements that have not yet been matched.

Example for assigning an array:

 type array_type is array(0 to 5) of std_logic_vector(7 downto 0); constant my_array : array_type := (0 => x"AB", 1 => x"CD", others => (others => '0'));