How to use 3-input logic gate in vhdl?

Question

I am just learning vhdl and trying to use 3 input nand keys. The code I have is:

G => (A nand B nand C) after 3 ns; 

but it does not compile.

Answer 1

I'm not an expert on VHDL, but I think you have a couple of errors - this should probably be:

 G <= not (A and B and C) after 3 ns; 

i.e. the destination is not in that direction, and I'm not sure that nand commutes as you need for the three inputs, hence using and for inputs, and then not to invert the output.

Answer 2

Oh, I think I know.

 G <= (A nand B nand C); 

You have an assignment operator sign, right?

Really delayed editing:

VHDL will not compile with the A nand B nand C syntax presented above, this gives a syntax error. It is best to do what Paul offers, and pull it out not to the logic.