CPUID: why should MISC_ENABLE.LCMV be set to 0 for some functions? Can I temporarily overwrite it?

Question

I am trying to use the CPUID, but there are some lines. According to sandpile.org CPUID page , standard CPUID functions 0000_0004h and above will only work if the MISC_ENABLE.LCMV flag is set to 0. This flag is bit 22 of the model specific register (MSR) 1A0. Apparently, this limitation is due to a bug in Windows NT (thanks for simplifying me, Microsoft;)).

I can check for the LCMV flag with CPUID 0000_0001h (ecx flags, bit 3). Assuming this is present, what exactly is it for, and why does it affect the CPUID? Is MSR 1A0 a read / write or read-only register? How is such a special register even read / written using assembler code?

If the register is technically read / written, is it safe to reset bit 22 to 0 for the duration of the CPUID command before restoring it to its original value? Or am I pretty tightened if it is installed incorrectly (that is, turned on)?

Finally, sandpile uses the wording: "This level is only allowed if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT error." If the group of standard levels is disabled for this reason, will it affect the output of the CPUID level of the level 0000_000h eax (maximum supported standard level)?

Fu ... I think about it.

Answer 1

You will need to download the Intel® 64 and IA-32 Architects Software Developer's Guides as it contains all the requested information.

I can check for the LCMV flag with CPUID 0000_0001h (ecx flags, bit 3). Assuming this is present, what exactly is it for, and why does it affect the CPUID?

The full flag name (see Volume 3B B-17 ) is "Limit CPUID MaxVal" and declares its effect as "When this bit is set to 1, CPUID.00H returns the maximum value in EAX [7: 0] of 3".

Is MSR 1A0 a read / write or read-only register?

Read / write in accordance with the Intel manual (with one caveat, read).

How can such a special register be read / written using assembly code?

You read using RDMSR (volume 2B 4-301) and write using WRMSR (volume 2B 4-505), but note that they require you to run either in real mode or in privilege mode 0 (aka kernel mode )

If the register is technically read / written, is it safe to reset bit 22 to 0 for the duration of the CPUID command before restoring it to its original value? Or am I pretty tightened if it is installed incorrectly (that is, turned on)?

It really should be installed only on buggy operating systems, and there you should not clean it. If you write your kernel in all ways, go ahead and clean it, as you yourself will set it out only for buggy versions of NT and similar circumstances.

Finally, sandpile uses the wording: "This level is enabled only if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT error." If the group of standard levels is disabled for this reason, will it affect the output of the CPUID level of the level 0000_000h eax (maximum supported standard level)?

Yes, it is specifically designed to force a return of 3 in this case (see above description).

Answer 2

I have only a little to add to the very detailed answer given above. (I would add it as a comment, but I cannot add comments yet.) An Intel engineer provided some more historical data on this subject at https://software.intel.com/en-us/forums/topic/306523?language= en # comment-1590394 Quote from there with minor corrections / spelling:

Some BIOS versions have a menu option that allows the user to limit the maximum value (or sheet index) that the CPUID will support after the next reboot. The BIOS provided this option solely to allow the end user to circumvent the Microsoft Windows * NT 4.0 installation problem because the Windows NT 4.0 installer had an error and would be blue if the CPUID reported that it supports leaves above 3. Enabling the BIOS option to limit CPUID EAax maxvalue values ​​of up to 3 are required only for installing Windows NT 4.0. In all other situations, the BIOS must be configured so as not to limit the maximum CPUID EAX.

When the CPUID is limited by the restriction that it does not support higher sheets than 3, on the Intel Pentium 4 processor and later, sheet 3 is also not supported, so the CPUID request to report sheet 4 will receive data from the CPUID on the sheet 2 (highest sheet index). When the software executes a CPUID with an invalid EAX input value (i.e., Sheet Index), the CPUID will report with the highest sheet that it supports in the current runtime configuration.

In addition, the MSR flag in question is called “IA32_MISC_ENABLE.BOOT_NT4 [bit 22]” in the current (June 2014) release of the Intel® 64 and IA-32 Software Developers Guide. I suspect that they decided to rename it at some point in order to make it more obvious that this is an obsolete issue that can be safely ignored today.