Verilog: is it possible to index an instance?

Question

I have a file something similar to

module AB(A,B,Out); input A,B; output Out; wire Out; assign Out = A & B; endmodule 

I need to use N number of these calculations. those. has a = 1001; b = 0001, I need to do something like bitwise AND, and I have N bits.

I used it as an instance:

 op[0] = a[0] & b[0]; op[1] = a[1] & b[1]; op[2] = a[2] & b[2]; op[3] = a[3] & b[3]; op[4] = a[4] & b[4]; 

When I try to do this with index i, I have:

 AB g(a[i],b[i],Op[i]) for i = 0 to N-1. 

If I do, he says that AB is not declared.

It's impossible? If so, what is the alternative?

Answer 1

You have several options:

• Bus size parameter in your module
• Array of instances
• generate

But to answer the question, you can do arrays of instances. Here is the syntax for your AB module.

 module testbench (); localparam WIDTH = 4; reg [WIDTH-1:0] a_in, b_in; wire [WIDTH-1:0] out_a; AB u0[WIDTH-1:0] ( .A(a_in), .B(b_in), .Out(out_a) ); initial begin ... end endmodule 

Here a_in[3] , b_in[3] and out_a[3] mapped to ports u0[3] .

Answer 2

This is possible using the generate statement, which supports an array of instances. This design was introduced in Verilog IEEE Std 1364-2001.

 genvar i; generate for (i=0; i<4; i=i+1) begin AB g (a[i], b[i], op[i]); end endgenerate