You have two problems with your gcc command line. First, you specify the -S flag, which causes gcc to emit assembly code, not object code. Secondly, you miss the -c flag, in which gcc compiles the file into an object file, but does not bind it. If you simply remove -S and do not change anything, you will get an executable program named file1.o and another named file2.o , not two object files.
Besides these errors, you can simplify your makefile with the help of template rules. I suggest you try the following:
all: exFile exFile: file1.o file2.o gcc -Wall -g -m32 $^ -o $@ %.o: %.c gcc -Wall -g -m32 -c $< -o $@ file1.o: file1.h
Or, as EmployedRussian points out, you can go with something even more minimal that uses more GNU make built-in functions:
CC=gcc CFLAGS=-Wall -g -m32 all: exFile exFile: file1.o file2.o $(LINK.c) $^ -o $@ file1.o: file1.h
source share