How to make VHDL "typedef"

Question

I want to "create" a type of "my_type", which is std_logic_vector (...), like this fake C / VHDL code: typedef std_logic_vector (CONSTANT downto 0) my_type.

"type" does not allow you to do this with std_logic_vector (...), only with an array, and "alias" uses only valid types, you cannot create a type with it.

So how to do this?

Answer 1

You need a subtype

subtype foo is std_logic_vector(7 downto 0);