Why do make files sometimes have "true <filename>" as part of the script assembly?

Question

For instance:

# Some stuff all: some dependencies @$(CC) -o foo.o foo.c @true foo.o @some other operation 

What is the purpose of the string "true foo.o"?

Answer 1

This is usually derived from a Makefile generator such as automake . true will be replaced by the actual command on platforms that require it. The most common case are platforms that do not support static archive indexes automatically; the code will look something like this:

 foo.a: foo.o bar.o baz.o ... ar rv foo.a foo.o bar.o baz.o ... true foo.a 

but on some platforms (without system or GNU ar ) it will be instead

 foo.a: foo.o bar.o baz.o ... ar rv foo.a foo.o bar.o baz.o ... ranlib foo.a 

The reason why it is not just deleted is that in m4 and other macro processors it is easier to replace text with a string than conditionally delete a string. (This can be done, but the advanced hacking m4 , as you know, is crazy. :)