This is not the best way to do this, but if you do it on these lines, write it as a shell condition without using the GNU make conditions:
$(TMPDIRPATH)%.o: %.cpp @echo compile $< @if [ $(notdir $<) != main.cpp ]; \ then $(COMPILE.cpp) $(OUTPUT_OPTION) $<; \ fi
Continuation markers required (backslashes). Similarly, semicolons. Values ββprefixed with $ will be extended to make before the shell is invoked to interpret them. You probably don't want the echo where it is. You probably need:
$(TMPDIRPATH)%.o: %.cpp @if [ $(notdir $<) != main.cpp ]; \ then echo compile $<; \ $(COMPILE.cpp) $(OUTPUT_OPTION) $<; \ fi
As I expected, this will be with a list of files that need to be compiled. Using any wild card mechanism leads to problems when adding additional files - other tests or roaming files that are not actually part of the system.
The comment says: "But the GNU Make Manual says that ifneq should work."
ifneq will work if it is placed correctly, which means "do not back down as part of the rule-related commands." So you could write something like (a terribly bad example, but my brain is on Fritz):
ifneq (${CFLAGS}, -Wall) CFLAGS += -Wall endif file1.o: file1.c ${CC} ${CFLAGS} -c $<
But when ifneq is indented, as in the question, it's just a command that is not actually found on the system when make launches a shell to process the command.
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