Xilinx ISE "Unable to directly access memory Q"

What is this mistake and what should I look for?

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I got this error when I did:

wire Q[3:0] , when I should have wire [3:0] Q;

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Errors are also common in Xilinx Vivado if you imported SystemVerilog code and did not specify the type of source code in the system navigator as such. Vivado by default does everything basic Verilog, and although almost everything in Verilog will be synthesized perfectly, if the file type is SystemVerilog, the opposite is not true.

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Source: https://habr.com/ru/post/1340836/


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