FPGA efficient (a) synchronous reset

Question

I remember that some time ago I read that either asynchronous or synchronous flushes are more efficiently implemented in FPGA, since a flip flop already has one, and the other will require additional logic.

Does anyone know in which direction this is happening? This is the same for Xilinx, Altera, Other ..

In training, I always added an asynchronous clear and synchronous reset to each FSM. Is there any benefit at all from this?

Thanks for any feedback!

Answer 1

Well, it is best to consult your specific document provider documentation and FPGA documents. In most of the professional design teams I worked on, we used asynchronous flushes to maintain maximum control. However, the choice between synchronous and asynchronous resets depends on your design and application.

By the way, you can find this dumping article from Sunburst Design interesting. Although it primarily deals with the design of ASIC and Verilog, it is useful for understanding reset solutions in general.

Answer 2

To directly answer the question - most FPGAs can perform synchronization or asynchronous reset in their triggers these days. Regarding the addition of asynchronous cleaning and synchronization, I'm not sure what you got from this - add the signals necessary for the function of your design (possibly including without reset at all for some failures ...)

Some additional tips ... If you use asynchronous reset, be very careful when you disable it. If there are a lot of distortions on this “slow” grid on your device, you may find some dips included in our reset system, to another clock cycle for others. Chaos is coming!

To avoid this, I recommend creating a top-level block that accepts your external (and supposedly very asynchronous) reset signal, synchronizes it with the clock, and passes it as a synchronous reset to all the flops you want to reset (in this watch domain - you can need more than one). Then the time analyzer will tell you that there is too much device skew, and you will make sure that everything immediately exits reset.

Xilinx has a white paper on this, but it also applies to other FPGAs.

For some applications, you may need an asynchronously declared reset in IO to ensure that some external devices work as you need, but disconnect it synchronously anyway.

(PS, since you mention FPGA, if you don't know, there is a stackexchange proposal related to programmable logic, which you can find in the interesting http://area51.stackexchange.com/proposals/20632/ )

Answer 3

The official position of Xilinx is to use reset synchronization. This is explained in this technical document , also mentioned in the above message. All Xilinx IP kernels shipped with source code, such as a memory controller, use reset synchronization.

My team experimented with different projects and found that the advantage of using sync reset in terms of improving the use of logic is not significant.

The biggest advantage of using async reset is faster builds, which is essential for large projects. The reason is that async reset paths are not covered by synchronous time limits (you can cover them by adding separate restrictions if you want).