VHDL Case Statements

Question

When programming in VHDL, can you use a variable in case case? This variable will be changed by one of the cases

i.e.

case task is when 1 => when 2 => when number => 

this is normal?

Answer 1

For modeling or synthesis?

In any case, from the documentation :

The choice must be constants of the same discrete type as the expression.

Use if to test number , or:

 if task=number then ... else case task is when 1 => ... when 2 => ... when others => ... end case; end if; 

or

 case task is when 1 => ... when 2 => ... when others => if task=number then ... else ... end if; end case; 

Your choice depends on whether you want the test result if task=number or the test when ... => take precedence? (for example, suppose for some reason number=1 do you want when 1 => or if task=number to ultimately provide your result?)

In the trivial case, the case synthesized as a multiplexer; the if synthesized as a comparator and a two-input multiplexer. One goes to the other.