What about the programmers "Invisible" registers?

Question

These are the "Programmer Visible" x86-64 registers:

_{(source: usenix.org )}

What about invisible registers? Only now I found out that the MMU registers, the interrupt descriptor table (IDT) uses these invisible registers. I learn these things the hard way. Is there any resource (book / documentation / etc.) that gives me a complete picture right away?

I am familiar with the programmer's visible registers and am comfortable in programming with them. I just want to learn about invisible registers and their functionality. I want to get the big picture. Where can I get this information?

EDIT:

I want to get the big picture. Where can I get this information?

These two books helped me understand all these low-level details.

1. Fundamentals of the organization and design of computers ~ Sivarama P. Dandamudi - 1st Edition (2003 )
2. Computer Organization and Design: Hardware-Software Interface, 4th Edition, ~ David A. Patterson, John L. Hennessy

Answer 1

IDT is an interrupt descriptor table that contains something like this from an abstract view, the first eighteen interrupts are reserved by the processor, and the next eighteen are reserved by Intel for future verification of the chip architecture ...

  Interrupt handler
    0 divide_by_zero_handler
    1 debug_handler
    .. ...
    13 general_exception_handler
    14 page_fault_handler
    .. ...
    18 machine_check_handler

In this context, handlers are part of the core of the toys, and each of the handlers is configured at boot time before loading custom land code. (BIOS is a 16-bit code, as well as a real-mode code), the kernel sets up handlers, switches to 32-bit protected mode when any of the interrupts is issued, the corresponding handler is executed depending on the interrupt number. For example, if interrupt 14 was created, the kernel will execute page_fault_handler , check if the page is dirty and on the disk, then load this page into memory, correct the addresses and clear the dirty bit, execute IRET the return command to continue, clear the flags ....

This is an abstract view of how IDT works ... Complex things happen behind the scenes ... depending on the architecture and type of memory management, such as addressing schemes with computed / flat / protected / virtual modes ...

Take a look at Intel documentation, which gives an excellent and complete overview of Intel programming ...

Edit: In the old days of DOS (which was 16-bit code and not very well protected from memory), it was possible to redirect interrupt handlers to their own handlers, thus imposing the original IDT on an example of such an interrupt, interrupt 9, which is an interrupt keyboard (BIOS interrupts in this context) using getvect(...) and setvect(...) calls, you can also handle some (not all processor interrupts, especially IDT 0 for division by zero) ... although these interrupts BIOS were pretty similar in appearance to interrupted I processor, they shared a common feature, both had the interrupt vector table (as it was then known). This is how TSR (Terminate Stay Resident) programs were able to save re-entry into DOS as a result of BIOS interrupt redirected to TSR handlers ...

Answer 2

You will need to read the processor reference guide for the particular processor you are interested in. Here is the Itanium Processor Reference Guide .