Patching gcc, adding memory, writing to sparc fsqrts insn

Question

I would like to correct the description of gcc sparc machine so that the destination register of the FPU operation sqareroot fsqrts is stored in memory after each fsqrts.

like this:

fsqrts %f2,%f4 st %f4, -4[%fp] <= add this after every fsqrts where -4[%fp] is a slot allocated on the stack for each fsqrts insn 

The sparc.md part that defines the fsqrts template:

 (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) 

I thought I could add " st %f4, -4[%fp] ". But now my question is:

• Where / when / how can I allocate a stack slot to save destination fpu reg in (offset to% fp).

I am not familiar with rtl presentation and compilation steps. Therefore any help would be appreciated.

Perhaps another architecture has a similar design that I can learn and use for my purpose. If someone can point me to such a part of the machine description ...

Answer 1

Again, what is the question for [e-mail]