After more than a day, looking at the tracks and the generated assembly, I think I understood this. The root cause problem turned out to be a design issue that only crashed if the ISR that started recording the serial port encountered a higher priority. It immediately became clear that you only need to add a few additional instructions in one cycle in order to cause conflicts between two interrupts.
So, the question arises: how to store, but not receive additional data in flash memory, cause additional instructions to execute?
The answer seems to be related to, but not quite the same as the suggestions of Frosty and Frederico. The new array moves some existing variables, but not across page borders or to slower regions (on this board, access time should be the same for all regions). But it changes the offsets of some commonly used structures, which forces the optimizer to issue slightly different sequences of commands to access them. One data alignment can stop the pipeline of one cycle, and the other does not. And these few instructions have shifted the synchronization enough to identify the underlying problem.
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