How to force the IAR to use the required Cortex-M0 + instructions (optimization will be disabled for this function).

Question

I need to force IAR tp to use some Cortex-M0 + instruction in some part of my code during encoding with C.

Please do not offer pure asm functions or inline asm etc.

I managed to do this for 51 instructions, but could not; ADR, BLX, RSBS, SBCS, SXTH.

Optimization is disabled for this function (#pragma optimization = none)

I tried many things, considering the behavior of teams. But the IAR prevailed with the same function with different instructions.

Has anyone struggled with such an unnecessary thing before, or does anyone have an idea?

Answer 1

Please do not offer pure asm functions or inline asm etc.

But this is the only solution to your problem that will not depend on the version of the compiler.

Maybe you

managed to do it for 51 instructions

.., but the next (main) version of the compiler may have a completely different idea on how to create instructions for your C code, even if the optimizer is turned off. BTDT for GCC.

Assembly language coding directly excludes this version of the dependecy compiler. You should even have some sample code, since most C-startup (reset handlers) are sent as assembler files.

Answer 2

In addition to BLX, which is not available on Corex, this code can get there. You may need to enable some optimizations.

char const * getstr(void) { return "ADR"; } long long llfunc(long long v1, long long v2) { return v1 - v2; } int neg(int i) { return -i; } void efunc(short); void func(short s) { efunc(s + 5); }