What is the LINT / synthesis statement to display an error at compile time?

Question

I have a module that is passed to parameter , and then creates another module that matches a specific parameter.

However, if the case is not defined for a specific combination of parameters, I would like a mistake to be made during compilation to highlight the problem, for example:

 generate if (PARAM1 == 1 && PARAM2 == 2) begin // instantiate module logic_A end else if (PARAM1 == 2 && PARAM2 == 1) begin // instantiate module logic_B end else begin // throw an error at compile time if we haven't // defined a case for those parameters end endgenerate 

However, this code still needs to be synthesized (in Verilog, not SystemVerilog) and skips LINTing, despite the error inserted.

Does anyone know what I can use in this situation? Thank you in advance.

Answer 1

I answered a very similar question on my sister's website, Electronics StackExchange, for a “ way to conditionally run a compile-time error in verilog . The solution is to conditionally create an instance of modules that do not exist. I recommend that a non-existent module have a very long name and meaningful name explains the error, this also reduces the risk that non-existent modules accidentally have the same name as an existing module.

 generate if (PARAM1 == 1 && PARAM2 == 2) begin : use_logicA // instantiate module logic_A end else if (PARAM1 == 2 && PARAM2 == 1) begin : use_logicB // instantiate module logic_B end else begin : illegal illegal_parameter_condition_triggered_will_instantiate_an non_existing_module(); end endgenerate 

This works because the verification of the existence of a non-existent module is not performed until the parameter values ​​are evaluated at the design stage.

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A better solution would be to use the SystemVerilog approach; especially with a simulator that complements the IEEE Std 1800-2009 or later standard. Then you can use $error() and give a more meaningful message to go with the error (for example, print the values ​​of the parameters that caused the error condition). You can learn more about this in IEEE Std 1800-2012 20.11 Development System Objectives

 generate if (PARAM1 == 1 && PARAM2 == 2) begin : use_logicA // instantiate module logic_A end else if (PARAM1 == 2 && PARAM2 == 1) begin : use_logicB // instantiate module logic_B end else begin : illegal $error("Expected PRAM1/2 to be 1/2 or 2/1, but was %0d/%0d", PARAM1, PARAM2 ); end endgenerate 

Answer 2

This is a bit awkward, and I don't know what your nap tool is checking, but what about this:

 generate if (PARAM1 == 1 && PARAM2 == 2) begin // instantiate module logic_A end else if (PARAM1 == 2 && PARAM2 == 1) begin // instantiate module logic_B end else begin reg ILLEGAL_VALUES_ON_PARAM1_AND_PARAM2; reg DUMMYO, DUMMYI; always @(posedge ILLEGAL_VALUES_ON_PARAM1_AND_PARAM2 or negedge ILLEGAL_VALUES_ON_PARAM1_AND_PARAM2) DUMMYO <= DUMMYI; end endgenerate 

This gives the following error in Quartus when I set PARAM1 to 3:

Error (10239): Verilog HDL always generates an error on synth_assertion.v (18): event management cannot check both positive and negative edges of the variable "ILLEGAL_VALUES_ON_PARAM1_AND_PARAM2"

Answer 3

Nope. There is nothing in verilog for this. You cannot do this when compiling.

But you can do something to reset errors and exit at “0” in the simulation.

In system verilog you can add a statement:

 initial assert(0) else $fatal("--error--"); 

or simply

 initial $fatal("--error--"); 

otherwise something like this:

  initial begin $display("--error--"); $finish; end 

Both will provide a message at the start of the simulation.