I designed a module and it has ram in it. Now I need several instances of this module in the top-level design, and each instance of the instance needs to be initialized with different content.
I checked quartus manual, it supports the use of $ readmemh to initialize ram. Therefore, I add two parameters to this module and pass it to other parameters so that I can guarantee that each instance reads different files.
This is my code, it works fine in modelsim, but when the synthesis in quartus, quartus crashes, and after I delete it, the synthesis of quartz is successful.
module cell_module #( parameter X_ID = "1", parameter Y_ID = "1", parameter DIR_ID = {X_ID, "_", Y_ID} ) ... reg [15:0] Mem_1 [0:31]; reg [15:0] Mem_2 [0:31]; `ifdef SIM_MEM_INIT initial begin $readmemh ({"../data", DIR_ID, "/file1.txt"},Mem_1); $readmemh ({"../data", DIR_ID, "/file2.txt"},Mem_2); end `endif
At the top level, I pass different parameters to each instance like this
cell_module #(.X_ID("1"), .Y_ID("1")) cell_module1 (...) cell_module #(.X_ID("1"), .Y_ID("2")) cell_module2 (...) cell_module #(.X_ID("2"), .Y_ID("1")) cell_module3 (...) cell_module #(.X_ID("2"), .Y_ID("2")) cell_module4 (...)
I have several folders doing this, each instance reads its own sets of files. I did not find that people like it, it works in modelsim, and quart analysis and successfully develops with it.
But this causes quartus_map to fail with synthsis. I can not find information about this error message.
If I cannot do this, are there any good methods for initializing a multiple instance of an instance with different content? Thanks
------------------------- update ------------------ p>
I built a small quartus project for testing. I followed the quartz guide to write a standard drum and modify it a bit, just added two parameters. This is the ram code,
module mem_init #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6, parameter X_ID = "1", Y_ID = "1", DIR_ID = {X_ID,"_", Y_ID}) (input [(DATA_WIDTH-1):0] data, input [(ADDR_WIDTH-1):0] addr, input we, clk, output [(DATA_WIDTH-1):0] q); reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; reg [ADDR_WIDTH-1:0] addr_reg; initial begin : INIT $readmemh ("../data", DIR_ID, "/file.txt", ram); end always @ (posedge clk) begin if (we) ram[addr] <= data; addr_reg <= addr; end assign q = ram[addr_reg]; endmodule
At the top level, I created an instance similar to this:
mem_init #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), .X_ID("1"), .Y_ID("1")) mem1 (.data(data1), .addr(add1), .we(we), .clk(clk), .q(q1)); mem_init #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), .X_ID("1"), .Y_ID("2")) mem2 ( .data(data2),.addr(add2),.we(we), .clk(clk), .q(q2));
this time quartus did not work, it was synthesized successfully. It seems that the quart allowed me to do this.