How should a timer interrupt be 0x08 if the first 32 interrupts are reserved for exceptions?

Question

I am developing a firmware for intel i386 and I am trying to figure out how to use a hardware timer. I read here (and other places) that the timer interrupt is 0x08, but this page (and various other sources) say that the first 32 interrupts are reserved for exceptions, and the 0x08 interrupt is specifically for a double error. What is the truth? How to configure a timer interrupt handler using either assembly or a very low C level without operating system calls?

I am developing a simple operating system to learn about the development of the operating system, so I do not have access to anything like Linux or system calls (unless I implement system calls myself. But creating a fully compatible POSIX OS is far beyond this project, so I would prefer to stick with simple, albeit slightly hacked solutions).

If that matters, I run it on QEMU, not on the physical i386.

Answer 1

Most people consider this (Timer using INT8) a design error in the original IBM PC architecture. To (partially) protect the perpetrators, the original 8088 did not really use this vector - it was, however, marked as “reserved" by Intel from the very beginning.

Before protected mode was invented, this conflict did not actually occur (CPUs <80286 did not use this double error). On most of today's PCs, 8259 PIC still exists, although not as a separate chip, but hidden somewhere in the PC chipset. Fortunately, INT08 to interrupt the timer is not cut at the hardware level, but rather initialized in the PIC of the computer BIOS. Thus, Protected Mode OS can easily rearrange PIC interrupts to other, more convenient places to avoid conflict. As far as I know, only DOS and other early operating systems assume a timer interrupt on INT8.