What does the PCOMMIT instruction do?

Question

In the Intel ISA Extension Guide, the description for pcommit little cryptic:

The pcommit command causes storage operations with memory to be stored in the ranges of read-only memory until they become permanent (protection against power failures). In particular, pcommit applies to stores that have been taken into memory .
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If pcommit is executed after storage in a constant range of memory is received into memory, storage becomes permanent when the pcommit character becomes globally visible.
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Data in the storage for permanent memory becomes permanent (durable) only after that it was either written to the target non-volatile device , or to some intermediate protection against storage / buffer failure.

He calls such concepts as constant ranges of memory, storages accepted in memory, preserves constancy and non-volatile device ¹ .

What is the exact context?

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¹ These cannot be classic NV devices, such as NOR Flash ROM or NVMe devices (read: new SSDs), because they are behind a variable number of bridges, including subtractive decoding ones, which the CPU does not control.

Answer 1

First of all, pcommit deprecated before it sent the actual processor .
Most of this answer is based on the content of the link above.

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Intel, together with Micron, has developed a new form of Non - Volatile Memory (NVM) called 3D XPoint (from its internal structure).
The actual implementation as a disk cache is already available, and Intel began to prepare for a wider implementation of its NVM technology some time ago.

In particular, Intel suggested that some DIMMs may contain parts created with 3D XPoint technology, and thus constitute a non-volatile device.

This will make one or more memory ranges permanent; collecting these constant ranges is called a constant domain.
One of the main features of a permanent domain is its ability to be secure from a security point of view.

When a store is created, it goes through:

• Storage buffer .
  The store is completed / visible locally, but not globally. The storage buffer can be sfence using various instructions (for example, sfence ).
• Cache hierarchy .
  The store is globally visible (cache coherence protocol provides this).
  The cache can be cleared with various instructions (e.g. clflush , clflushopt , clwb , etc.).
• Write Pending Queue (WPQ) memory controller .
  The store is accepted in memory, but it is not yet written in DIMM.
  WPQ can be cleared through specific PCIe configuration registers of the memory controller or using pcommit .
• The memory .
  The storage is committed / recorded in memory.

At what point in the data path above the storage is in the permanent domain and therefore it will not be lost in the event of a power failure?
Some memory controllers have the Asynchronous DRAM Refresh feature, which ensures that even in the event of power loss, the WPQ will be properly cleaned (for example, from the battery).
For these platforms, the persistent domain begins with WPQ.

Intel, however, is concerned that not all platforms would have the ADR feature and created the pcommit instruction as a way to verify that a storage domain has been entered into the repository ( pcommit is user-executable).

Thus, it is assumed that the storage should be permanent.

 mov [X], rax ;Store ;Here the store has started moving to the store buffer clwb [X] ;Here the store has moved to the cache (CLWB is ordered with previous stores) ;and then starting moving to the memory controller WPQ ;(the line containing X has been written back) sfence ;Wait for CLWB to become globally visible ;Here the store is in the WPQ pcommit ;The store is being committed sfence ;Wait for pcommit to become globally visible ;The store is committed 

It turned out that every platform that plans to support the new Intel NVM technology also plans to support ADR, so Intel has deprecated pcommit in favor of a simpler programming model:

 mov [X], rax clwb [X] sfence ;Here the store is in the WPQ and that enough