How to use arrays (representing buses) in HDL?
For example, I have the following code:
CHIP And16 { IN a[16], b[16]; OUT out[16]; PARTS:
Assuming I already have And , how could I implement this?
I would prefer not to have the following:
And(a=a[0],b=b[0],out=out[0]); And(a=a[1],b=b[1],out=out[1]); ... And(a=a[14],b=b[14],out=out[14]); And(a=a[15],b=b[15],out=out[15]);
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