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Is there any recommended way to automate the connection to the module port?

I am trying to understand or explore the best ASIC design practices in verilog. I am working on a medium-sized block with ~ 20 auxiliary modules (each 1000 lines of code). It is a painstaking task to manually create an instance of the entire submodule and make a connection to the port to create a top-level RTL.

I want to write a script to automate this. As long as we can determine the input / output data of all submodules and how each of the submodules is related to each other, it should not be too difficult to automatically generate a top level. However, I do not have enough experience in design automation. I was wondering if anyone could give me some guidance on how to get started.

  • Is there any open source tool to achieve what I'm trying to do? I haven't found it yet.
  • Is there any standardized way to generate synthesized code of this kind?

I appreciate any material or advice.

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Depending on which text editor you use, you may use some pre-existing tools. Emacs has an add-in that supports the automatic creation and connection of signals, assuming that you follow certain naming conventions:

http://www.veripool.org/wiki/verilog-mode/Verilog-mode_veritedium

For vim users, there are several plugins that allow you to use an Emacs script, for example this one:

http://www.vim.org/scripts/script.php?script_id=1875

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Source: https://habr.com/ru/post/1246668/

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