The sequence of microoperations for operations?

Question

Consider the following sequence of microoperations.

MBR ← PC MAR ← X PC ← Y Memory ← MBR 

Which of the following is a possible operation performed by this sequence?

• Team selection
• Operand fetch
• Conditional branch
• Initiation of the interrupt service

---

The answer is option (4).

My attempt:

• Choosing a command: Fetch command: read the instruction code from an address on a PC and put it in the infrared port. (IR ← Memory [PC])
• Operand fetch: select operands from memory if necessary: ​​if any operands are memory addresses, initiate a memory read cycle to read them into processor registers. If the operand is in memory, and not in the register, then the memory address of the operand is known as an effective address or advisor for short. Therefore, the selection of the operand can be designated as Register ← Memory [EA]. On today's computers, processors are much faster than memory, so sampling from operands usually requires several clock cycles.
• The conditional branch instruction causes the location counter in the PSW to be set to the address specified in the register or register plus a 12-bit offset if the condition is met (and the register is not 0)
• An interrupt service routine (ISR) is a software routine that the hardware calls in response to an interrupt. ISRs examine the interrupt and determine how to handle it. ISRs handle the interrupt and then return the logical interrupt value.

---

Can you explain the sequence of micro-operations for the operations indicated in the options?

Answer 1

This question uses a notation from a single textbook textbook by William Stolling Computer Organization and Architecture . The question itself does not contain sufficient background material for someone unfamiliar with the Stalling textbook to answer it (I do not own the Stalling textbook or do not know which version this question refers to).

However, after seeing a comment indicating a response on another site , I googled for the "clock cycle grouping rules." This led to a bunch of links that pointed to various different slides.

The third link for me was a PowerPoint presentation , which included a slide, which I copied below as an image. There was a slide that explained what MAR and MBR mean:

Memory Address Register (MAR)

• Connected to Address Bus

• Specifies the address to read or write op

Memory Buffer Register (MBR)

• Connected to data bus

• Holds data to write or read recent data.

So, it seems that what happens is that the PC first fits in the MBR . Then the address where the PC will be saved will be copied from X to MAR . In the same loop, the PC set to the beginning of the interrupt service routine available in Y Finally, the data in the MBR transmitted over the bus to memory.