Why is my virtual memory entry not showing up in the virtual device driver?

Question

I have a custom driver that I wrote to make it easy to custom map exact RAM RAM addresses to user land. I am trying to verify that the mmap'd shared memory is split between two processes on the same hardware address, which facilitates the visible memory operations that each side can see.

My code is something like this:

//placement: in a mmap callback to a file_operations facilitated // character device //phys_addr - a variable that I will ioremap for a virtual addr virtaddr = ioremap(phys_addr, size); if (!virtaddr) { printk(KERN_INFO "could not remap page!"); goto out; } else { printk(KERN_INFO "attempting write"); *((int *)virtaddr) = 0xdeadbeef; //wmb(); <--- I haven't tried this yet } 

Be that as it may, I thought that perhaps the problem was the lack of a write barrier to make the cache flush to the ram. I have to download the test on some special hardware due to OS features that go beyond the scope of this question. I do not think that write barriers are applicable to main memory or plungers, as well as for device registers or device memory (for example, cache on SSD or something else). So, I did not test wmb, but I just wanted to get my question. I searched around for some, as well as through the Linux 3 device driver book, and I executed my code; the fragment from which I draw is actually executed, and I know this because I see the print. The driver executes the code, but then just continues to work. Finally, there is a similar part of the code that runs on ioremap on the common part of the hardware memory, which it then tries to read. This read does not contain the meaning that I wrote to him.

Why?

Answer 1

Could you tell us exactly what you mean by this statement "memory address of the hardware RAM memory in user land".

What type of device are you simulating [PCIe, USB, etc.]

It all depends on your processor routing and, since the hardware is not connected, then the transfer will not fail, instead it will send data via the bus protocol, which will be just like fake packaged generation from the bus controller to the device.

To verify that you can verify bus transactions, and in the case of matching I / O ports, you can check the use of signals coming from a specific port address / bits.