How is a 32-bit instruction for holding IR bits? (32-bit RISC architecture)

Question

I was a bit confused with the size and address space (I suggested that the size of the instruction should be the same as the size of the address bits. In my book I did not find a sufficient explanation). If I’m right, then theoretically, if we have 2 ^ 32 addressable units (bytes) of memory in a 32-bit architecture (RISC style), as in the load instruction of 4 bytes in size, as well as in the address?

Answer 1

You assume that one command can encode a load from an arbitrary absolute address. This is true for x86, even in 64-bit mode (but there is a special operation code for loading from a 64-bit absolute address without movement or index registers, and dest should be rax).

On most RISC architectures, loading from an absolute address is usually done using two immediate mov commands to set the upper and lower half of the register, and then use that register as the address for the load.

For instance,

int a; int foo(void) { return a; } 

compiles (ARM gcc 4.8.2 on godbolt) :

 foo(): movw r3, #:lower16:.LANCHOR0 @ tmp113, movt r3, #:upper16:.LANCHOR0 @ tmp113, ldr r0, [r3] @, a bx lr @ a: .space 4 

Answer 2

For memory access instructions, instructions typically use an address register with an offset. Something like a form: load R1, [R2 + 8] . ARM, x86, MIPS and many others offer this mode. It is often possible to use a PC as an address register in order to be able to display the constants that are next to the code.

For jump instructions, in addition to using the address register, you often have an offset that does not use any register, but jumps the X instructions forward or backward. The offset is usually limited in the range and can be shifted by a certain amount (limiting addresses that are multiples of 2, 4 ...), so it can fit into a small direct operand.
MIPS also uses a combination between absolute and relative jumps: the j command goes to the absolute address, but in the area of ​​the current instruction. To be precise, the immediate address is missing a few high bits (so that it can fit), and use the high bits of the current PC instead.

Answer 3

You can encode a 32-bit instantaneous value in a 4-byte instruction, limiting the number of values ​​that can be represented in a range.

ARM does this by encoding 8 bits at once, plus an additional 4-bit field that indicates rotation. The CPU calculates the immediate value by taking these 8 bits and rearranging them the number of times indicated by the 4-bit field.

Answer 4

And one more trick (ARM also uses a version of this): if the command address should be aligned by 4 bytes, do not include the two least significant bits - they should be zero. You have 2 bits for the opcode.

And some processors do not support absolute addresses as integral elements, but only long relative offsets. These systems use trampolines for longer jumps.