Android processor register names?

Question

This piece of code is extracted from the Android crash report on the Samsung S tab:

Build fingerprint: 'samsung/chagallwifixx/chagallwifi:5.0.2/LRX22G/T800XXU1BOCC:user/release-keys' Revision: '7' ABI: 'arm' r0 a0d840bc r1 a0dcb880 r2 00000001 r3 a0d840bc r4 a0dc3c4c r5 00000000 r6 a066d200 r7 00000000 r8 32d68f40 r9 a0c359a8 sl 00000014 fp bef3ba84 ip a0dc3fb8 sp bef3ba10 lr a0c35a0c pc a0c34bc8 cpsr 400d0010 

r0 through r9 are quite distinct general-purpose registers, sp ( r13 ) is the stack pointer, and pc ( r15 ) is the program counter (instruction pointer). Referring to the Wikipedia ARM archiving page in the "Registers" section (one of the many pages that I looked through), I found that lr ( r14 ) is the link register and cpsr is the "Current program status register".

I would like to know that sl ( r10 ), fp ( r11 ) and ip ( r12 ). I expect ip not an "instruction pointer" because this function is executed by pc ( r15 ).

Is there a reference document that I have not found that illustrates these names?

Answer 1

The current standard ARM EABI procedure call describes the standard "special" names for r12-r15:

• PC (r15): program counter
• LR (r14): reference register
• SP (r13): stack pointer
• IP (r12): intra-zero register ^*

GNU tools still support legacy obsolete APCS names as identifiers for given register numbers, although they no longer necessarily have what it means:

• FP (r11): frame pointer - may still be true for ARM code; Thumb code tends to keep the actual frame pointers in r7, and of course the code can be compiled without frame pointers at all, in which cases "fp" is just another general register registered with the chat.
• SL (r10): Stack restriction - I don’t really know the history of this, but in most modern codecs, r10 is no more special than r4-r8.

Note that r9 is not necessarily a general-purpose register - EABI reserves it for specific platform purposes. In linux-gnueabi, this is nothing special, but other platforms can use it for special purposes, such as a TLS pointer or a global object table, so it can also be replaced with SB (static base) or TR (stream register).

_{* Story that there is a limited range of branch instructions from the PC - if the linker finds that the call target ends in more than 32 MB, it can generate a veneer (some additional instructions within the range of the call site) as a branch target that calculates the real address and executes an absolute branch, which may require a zero register.}