Using loop generation in verilog

Question

I am trying to understand why we use generate in verilog along with the for loop.

Using the generate and for loop:

reg [3:0] temp; genvar i; generate for (i = 0; i < 3 ; i = i + 1) begin: always @(posedge sysclk) begin temp[i] <= 1'b0; end end endgenerate 

Use only for loop:

 reg [3:0] temp; genvar i; always @(posedge sysclk) begin for (i = 0; i < 3 ; i = i + 1) begin: temp[i] <= 1'b0; end end 

I consider that two fragments will basically produce the same result, i.e. temp [0] to temp [10], equal to the value 0. What is the difference / advantage that we see using the generate operator in this case?

Answer 1

In general, the main difference between the generation cycles for the cycle and the regular cycle is that the generate cycle for the cycle generates an instance for each iteration. This means that in your example there will always be 3 blocks (as opposed to 1 block in the case of a regular loop).

A good example of the code you need is:

 module A(); .. endmodule; module B(); parameter NUM_OF_A_MODULES = 2; // should be overriden from higher hierarchy genvar i; for (i=0 i<NUM_OF_A_MODULES; i=i+1) { A A_inst(); } endmodule; 

In this example, a regular value cannot do the job of instantiating NUM_OF_A_MODULES.

In your example, you can get the desired result in both directions. (while you fix some minor bugs :))

Answer 2

In the example without generate , i should be genvar not integer . Otherwise, both values ​​are valid depending on the version of IEEE Std 1364 supported by your toolbox. The generation construct was added to IEEE Std 1364-2001, where the generate / endgenerate keywords are explicitly required. In IEEE Std 1364-2005, it became optional with the only requirement that if generate used, it must have an appropriate endgenerate .

When using IEEE Std 1364-2005 or SystemVerilog (IEEE Std 1800), this is a matter of preference for the coding style of the implicit vs explicit declaration. The explicit has the advantage of having backward comparability.

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Generate blocks are useful when changing the physical structure of the module after using the parameters. For example, select inactive or set hours and enable only one:

 if ( param_use_pos == 1) begin : use_pos always @(posedge sysclk) begin ... end end else begin : use_neg always @(negedge sysclk) begin ... end end 

If you do not change the physical structure, it is usually better to use it for loops and if-else statements inside an always block. Both approaches can synthesize the same thing, but when you start RTL modeling, an inefficient block approach will tend to simulate faster. This is because simulators can usually process one N-bit operation faster than N 1-bit operations. Synthesis again is the same result.

 // faster :: 1 always block, simulator can optimize the for loop always @(posedge sysclk) begin for (i = 0; i < 3 ; i = i + 1) begin temp[i] <= 1'b0; end end // slower :: creates 4 always blocks, harder for the simulator to optimize genvar i; generate // optional if > *-2001 for (i = 0; i < 3 ; i = i + 1) begin always @(posedge sysclk) begin temp[i] <= 1'b0; end end endgenerate // match generate