I am writing a Makefile with a lot of repetitive things, for example.
debug_ifort_Linux: if [ $(UNAME) = Linux ]; then \ $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..." \ TARGET=$@ LEXT="ifort_$(UNAME)" -e syst; \ else \ echo $(err_arch); \ exit 1; \ fi
where the target "syst" is defined, the variable "UNAME" is defined (and usually it is Linux, but can also be Cygwin or OSF1), and the "difort" and "err_arch" variables are defined. This block of code is used so many times for different purposes of the compiler (using the naming convention ''). Since this is a huge amount of redundant code, I would like to write it in a simpler way. For example, I would like to do something like this:
debug_ifort_Linux: compile(uname,compiler,flags,petsc_flags,target,lext)
where compilation can be a function that executes the code above based on the arguments. Does anyone know how I could do this?
function bash makefile gnu-make
Karl Yngve LervΓ₯g Feb 03 '09 at 15:47 2009-02-03 15:47
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