Add variables to GNU make via command line

Question

I am using the GNU-make Makefile to create a C project with several goals ( all , clean and several target projects). During the debugging process, I would like to add several flags to the same assembly without constantly editing the Makefile (for example, add debugging symbols or set the preprocessor flag).

In the past, I did this as follows (using an example of debugging symbols):

 make target CFLAGS+=-g 

Unfortunately, this is not an addition to the CFLAGS variable, but instead cleans up and stops compiling it. Is there a clean way to do this without specifying some dummy variable added at the end of CFLAGS and LDFLAGS ?

Answer 1

Check override directive . You may have to modify the makefile once, but it should do what you want.

Example makefile:

 override CFLAGS += -Wall app: main.c gcc $(CFLAGS) -o app main.c 

Command line example:

 $ make gcc -Wall -o app main.c $ make CFLAGS=-g gcc -g -Wall -o app main.c 

Answer 2

For the record, @Carl Norum's answer adds a variable from the command line perspective.

I needed a way to add and come up with:

 override CFLAGS := -Wall $(CFLAGS) 

Answer 3

There are two ways to pass variables:

• Using command line arguments:

   make VAR=value 

• Using environment:

   export VAR=var; make 

  or (better, because it only changes the environment for the current command)

   VAR=var make 

They are a little different. The first is stronger. That means you know what you want. The second can be considered a hint. The difference between the two is in the = and += operators (without override ). These statements are ignored when the variable is defined on the command line, but not ignored when the variable is defined in the environment. So, I suggest you have a Makefile with:

 CC ?= gcc CFLAGS += -Wall INTERNAL_VARS = value 

and call it with:

 CFLAGS=-g make 

Please note that if you want to remove -Wall , you can use:

 make CFLAGS= 

Please do not use the override keyword, otherwise you will have no way to change the variable affected by override .

Answer 4

Just notice how confused I am - let it be a testmake file:

 $(eval $(info A: CFLAGS here is $(CFLAGS))) override CFLAGS += -B $(eval $(info B: CFLAGS here is $(CFLAGS))) CFLAGS += -C $(eval $(info C: CFLAGS here is $(CFLAGS))) override CFLAGS += -D $(eval $(info D: CFLAGS here is $(CFLAGS))) CFLAGS += -E $(eval $(info E: CFLAGS here is $(CFLAGS))) 

Then:

 $ make -f testmake A: CFLAGS here is B: CFLAGS here is -B C: CFLAGS here is -B D: CFLAGS here is -B -D E: CFLAGS here is -B -D make: *** No targets. Stop. $ make -f testmake CFLAGS+=-g A: CFLAGS here is -g B: CFLAGS here is -g -B C: CFLAGS here is -g -B D: CFLAGS here is -g -B -D E: CFLAGS here is -g -B -D make: *** No targets. Stop. 

With override directives removed from the testmake file:

 $ make -f testmake A: CFLAGS here is B: CFLAGS here is -B C: CFLAGS here is -B -C D: CFLAGS here is -B -C -D E: CFLAGS here is -B -C -D -E make: *** No targets. Stop. $ make -f testmake CFLAGS+=-g A: CFLAGS here is -g B: CFLAGS here is -g C: CFLAGS here is -g D: CFLAGS here is -g E: CFLAGS here is -g make: *** No targets. Stop. 

So,

• If a variable is used by override once, it can only be added using another statement using override (normal assignments will be ignored);
• when there was no override ; trying to add (as in += ) from the command line, overwrites each instance of this variable.